Lead ASIC DFT Engineer

Role overview Lead design-for-test architecture, implementation, verification, debug, and sign-off for complex ASIC and SoC designs. Responsibilities - Own DFT architecture, scan insertion, scan-chain stitching, compression, and coverage closure. - Lead MBIST/LBIST integration, verification, and debug. - Develop and validate DFT constraints, SDC, timing checks, simulations, DRC, diagnosis, and failure analysis. - Collaborate with RTL, verification, physical design, STA, and silicon validation teams. - Mentor engineers and build automation using TCL, Perl, or Python. Requirements - Significant hands-on ASIC DFT experience. - Strong scan, ATPG, MBIST, LBIST, JTAG, boundary scan, iJTAG, SSN, fault models, silicon debug, major EDA tool flows, RTL, synthesis, LEC, STA, and post-silicon validation experience.